1. Field of the Invention
The present invention relates to computer systems using a bus bridge(s) to interface a central processor(s), video graphics processor(s), random access memory and input-output peripherals together, and more particularly, to a multi-mode graphics address remapping table (GART) used with an accelerated graphics port device.
2. Description of the Related Art
Use of computers, especially personal computers, in business and at home is becoming more and more pervasive because the computer has become an integral tool of most information workers who work in the fields of accounting, law, engineering, insurance, services, sales and the like. Rapid technological improvements in the field of computers have opened up many new applications heretofore unavailable or too expensive for the use of older technology mainframe computers. These personal computers may be stand-alone workstations (high end individual personal computers), desk-top personal computers, portable lap-top computers and the like, or they may be linked together in a network by a xe2x80x9cnetwork serverxe2x80x9d which is also a personal computer which may have a few additional features specific to its purpose in the network. The network server may be used to store massive amounts of data, and may facilitate interaction of the individual workstations connected to the network for electronic mail (xe2x80x9cE-mailxe2x80x9d), document databases, video teleconferencing, white boarding, integrated enterprise calendar, virtual engineering design and the like. Multiple network servers may also be interconnected by local area networks (xe2x80x9cLANxe2x80x9d) and wide area networks (xe2x80x9cWANxe2x80x9d).
A significant part of the ever increasing popularity of the personal computer, besides its low cost relative to just a few years ago, is its ability to run sophisticated programs and perform many useful and new tasks. Personal computers today may be easily upgraded with new peripheral devices for added flexibility and enhanced performance. A major advance in the performance of personal computers (both workstation and network servers) has been the implementation of sophisticated peripheral devices such as video graphics adapters, local area network interfaces, SCSI bus adapters, full motion video, redundant error checking and correcting disk arrays, and the like. These sophisticated peripheral devices are capable of data transfer rates approaching the native speed of the computer system microprocessor central processing unit (xe2x80x9cCPUxe2x80x9d). The peripheral devices"" data transfer speeds are achieved by connecting the peripheral devices to the microprocessor(s) and associated system random access memory through high speed expansion local buses. Most notably, a high speed expansion local bus standard has emerged that is microprocessor independent and has been embraced by a significant number of peripheral hardware manufacturers and software programmers. This high speed expansion bus standard is called the xe2x80x9cPeripheral Component Interconnectxe2x80x9d or xe2x80x9cPCI.xe2x80x9d A more complete definition of the PCI local bus may be found in the PCI Local Bus Specification, revision 2.1; PCI/PCI Bridge Specification, revision 1.0; PCI System Design Guide, revision 1.0; PCI BIOS Specification, revision 2.1, and Engineering Change Notice (xe2x80x9cECNxe2x80x9d) entitled xe2x80x9cAddition of xe2x80x98New Capabilitiesxe2x80x99 Structure,xe2x80x9d dated May 20, 1996; and the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0, dated Sep. 22, 1999, the disclosures of which are hereby incorporated by reference. These PCI specifications and ECN are available from the PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214.
A computer system has a plurality of information (data and address) buses, such as a host bus, a memory bus, at least one high speed expansion local bus such as the PCI bus, and other peripheral buses such as the Small Computer System Interface (SCSI), Extension to Industry Standard Architecture (EISA), and Industry Standard Architecture (ISA). The microprocessor(s) of the computer system communicates with main memory and with the peripherals that make up the computer system over these various buses. The microprocessor(s) communicates to the main memory over a host bus to memory bus bridge. The peripherals, depending on their data transfer speed requirements, are connected to the various buses which are connected to the microprocessor host bus through bus bridges that detect required actions, arbitrate, and translate both data and addresses between the various buses.
Increasingly sophisticated microprocessors have revolutionized the role of the personal computer by enabling complex applications software to run at mainframe computer speeds. The latest microprocessors have brought the level of technical sophistication to personal computers that, just a few years ago, was available only in mainframe and mini-computer systems. Some representative examples of these new microprocessors are the xe2x80x9cPENTIUMxe2x80x9d and xe2x80x9cPENTIUM PROxe2x80x9d (registered trademarks of Intel Corporation). Advanced microprocessors are also manufactured by Advanced Micro Devices, Cyrix, IBM, Digital Equipment Corp., and Motorola.
These sophisticated microprocessors have, in turn, made possible running complex application programs using advanced three dimensional (xe2x80x9c3-Dxe2x80x9d) graphics for computer aided drafting and manufacturing, engineering simulations, games and the like. Increasingly complex 3-D graphics require higher speed access to ever larger amounts of graphics data stored in memory. This memory may be part of the video graphics processor system, but, preferably, would be best (lowest cost) if part of the main computer system memory. Intel Corporation has proposed a low cost but improved 3-D graphics standard called the xe2x80x9cAccelerated Graphics Portxe2x80x9d (AGP) initiative. With AGP 3-D, graphics data, in particular textures, may be shifted out of the graphics controller local memory to computer system memory. The computer system memory is lower in cost than the graphics controller local memory and is more easily adapted for a multitude of other uses besides storing graphics data.
The proposed Intel AGP 3-D graphics standard defines a high speed data pipeline, or xe2x80x9cAGP bus,xe2x80x9d between the graphics controller and system memory. This AGP bus has sufficient bandwidth for the graphics controller to retrieve textures from system memory without materially affecting computer system performance for other non-graphics operations. The Intel 3-D graphics standard is a specification which provides signal, protocol, electrical, and mechanical specifications for the AGP bus and devices attached thereto. This specification is entitled xe2x80x9cAccelerated Graphics Port Interface Specification Revision 1.0,xe2x80x9d dated Jul. 31, 1996, (xe2x80x9cAGP1.0xe2x80x9d) the disclosure of which is hereby incorporated by reference. Enhancements to the AGP1.0 Specification are included in the xe2x80x9cAccelerated Graphics Port Interface Specification Revision 2.0,xe2x80x9d dated May 4, 1998 (xe2x80x9cAGP2.0xe2x80x9d), the disclosure of which is hereby incorporated by reference. Both the AGP1.0 and AGP2.0 Specifications are available from Intel Corporation, Santa Clara, Calif.
The AGP1.0 interface specification uses the 66 MHz PCI (Revision 2.1) specification as an operational baseline, with three performance enhancements to the PCI specification which are used to optimize the AGP1.0 Specification for high performance 3-D graphics applications. These enhancements are: 1) pipelined memory read and write operations, 2) demultiplexing of address and data on the AGP bus by use of sideband signals, and 3) data transfer rates of 133 MHz for data throughput in excess of 500 megabytes per second (xe2x80x9cMB/sxe2x80x9d). The remaining AGP1.0 Specification does not modify the PCI specification, but rather provides a range of graphics-oriented performance enhancements for use by 3-D graphics hardware and software designers. The AGP1.0 Specification is neither meant to replace nor diminish full use of the PCI standard in the computer system. The AGP1.0 Specification creates an independent and additional high speed local bus for use by 3-D graphics devices such as a graphics controller, wherein the other input-output (xe2x80x9cI/Oxe2x80x9d) devices of the computer system may remain on any combination of the PCI, SCSI, EISA and ISA buses. The AGP1.0 Specification supports only 32-bit memory addressing.
The AGP2.0 Specification supports 64-bit memory addressing, which is beneficial for addressing memory sizes allocated to the AGP device that are larger than 2 GB. The AGP2.0 Specification also includes several other enhancements. For example, the AGP2.0 Specification supports 1) 4xc3x97 transfer mode with low (1.5V voltage electrical signals that allows four data transfers per 66 MHz clock cycle, providing data throughput of up to 1 GB/second; 2) five additional sideband signals; 3) a fast write protocol; 4) new input/output buffers; and 5) new mechanical connectors.
Regardless of the version of the AGP specification, to functionally enable the AGP 3-D graphics bus, new computer system hardware and software are required. This requires new computer system core logic designed to function as a host bus/memory bus/PCI bus to AGP bus bridge meeting the AGP1.0 or AGP2.0 Specifications, and new Read Only Memory Basic Input Output System (xe2x80x9cROM BIOSxe2x80x9d) and Application Programming Interface (xe2x80x9cAPIxe2x80x9d) software to make the AGP dependent hardware functional in the computer system. The computer system core logic must still meet the PCI and/or PCI-X standards referenced above and facilitate interfacing the PCI bus(es) to the remainder of the computer system. In addition, new AGP compatible device cards must be designed to properly interface, mechanically and electrically, with the AGP bus connector.
A major performance/cost enhancement using AGP in a computer system is accomplished by shifting texture data structures from local graphics memory to main memory. Textures are ideally suited for this shift for several reasons. Textures are generally read-only, and therefore problems of access ordering and coherency are less likely to occur. Shifting of textures serves to balance the bandwidth load between system memory and local graphics memory, since a well-cached host processor has much lower memory bandwidth requirements than does a 3-D rendering machine; texture access comprises perhaps the single largest component of rendering memory bandwidth, so avoiding loading or caching textures in local graphics memory saves not only this component of local memory bandwidth, but also the bandwidth necessary to load the texture store in the first place, and, further, this data must pass through main memory anyway as it is loaded from a mass store device. Texture size is dependent upon application quality rather than on display resolution, and therefore may require the greatest increase in memory as software applications become more advanced. Texture data is not persistent and may reside in the computer system memory only for the duration of the software application, so any system memory spent on texture storage can be returned to the free memory heap when the application concludes (unlike a graphic controller""s local frame buffer which may remain in persistent use). For these reasons, shifting texture data from local graphics memory to main memory significantly reduces computer system costs when implementing 3-D graphics.
Generally, in a computer system memory architecture the graphics controller""s physical address space resides above the top of system memory. The graphics controller uses this physical address space to access its local memory which holds information required to generate a graphics screen. In the AGP system, information still resides in the graphics controller""s local memory (textures, alpha, z-buffer, etc.), but some data which previously resided in this local memory is moved to system memory (primarily textures, but also command lists, etc.). The address space employed by the graphics controller to access these textures becomes virtual, meaning that the physical memory corresponding to this address space doesn""t actually exist above the top of memory. In reality, each of these virtual addresses corresponds to a physical address in system memory. The graphics controller sees this virtual address space, referenced hereinafter as xe2x80x9cAGP device address space,xe2x80x9d as one contiguous block of memory, but the corresponding physical memory addresses may be allocated in 4 kilobyte (xe2x80x9cKBxe2x80x9d), non-contiguous pages throughout the computer system physical memory.
There are two primary AGP usage models for 3D rendering that have to do with how data are partitioned and accessed, and the resultant interface data flow characteristics. In the xe2x80x9cDMAxe2x80x9d model, the primary graphics memory is a local memory referred to as local frame buffer and is associated with the AGP graphics controller or xe2x80x9cvideo accelerator.xe2x80x9d 3D structures are stored in system memory, but are not used (or xe2x80x9cexecutedxe2x80x9d) directly from this memory; rather they are copied to primary (local) memory, to which the rendering engine""s address generator (of the AGP graphics controller) makes references thereto. This implies that the traffic on the AGP bus tends to be long, sequential transfers, serving the purpose of bulk data transport from system memory to primary graphics (local) memory. This sort of access model is amenable to a linked list of physical addresses provided by software (similar to operation of a disk or network I/O device), and is generally not sensitive to a non-contiguous view of the memory space.
In the xe2x80x9cexecutexe2x80x9d model, the video accelerator uses both the local memory and the system memory as primary graphics memory. From the accelerator""s perspective, the two memory systems are logically equivalent; any data structure may be allocated in either memory, with performance optimization as the only criteria for selection. In general, structures in system memory space are not copied into the local memory prior to use by the video accelerator, but are xe2x80x9cexecutedxe2x80x9d in place. This implies that the traffic on the AGP bus tends to be short, random accesses, which are not amenable to an access model based on software resolved lists of physical addresses. Since the accelerator generates direct references into system memory, a contiguous view of that space is essential. But, since system memory is dynamically allocated in, for example, random 4,096 byte blocks of the memory, hereinafter 4 kilobyte (xe2x80x9cKBxe2x80x9d) pages, the xe2x80x9cexecutexe2x80x9d model provides an address mapping mechanism that maps the random 4 KB pages into a single contiguous address space.
The AGP Specification supports both the xe2x80x9cDMAxe2x80x9d and xe2x80x9cexecutexe2x80x9d models. However, since a primary motivation of the AGP is to reduce growth pressure on the graphics controller""s local memory (including local frame buffer memory), the xe2x80x9cexecutexe2x80x9d model is preferred. Consistent with this preference, the AGP Specification requires a virtual-to-physical address re-mapping mechanism which ensures the graphics accelerator (AGP master) will have a contiguous view of graphics data structures dynamically allocated in the system memory. This address re-mapping applies only to a single, programmable range of the system physical address space and is common to all system agents. Addresses falling in this range are re-mapped to non-contiguous pages of physical system memory. All addresses not in this range are passed through without modification, and map directly to main system memory, or to device specific ranges, such as a PCI device""s physical memory. Re-mapping is accomplished via a xe2x80x9cGraphics Address Remapping Tablexe2x80x9d (xe2x80x9cGART tablexe2x80x9d) which is set up and maintained by a GART miniport driver software, and used by the core logic chipset to perform the re-mapping. In order to avoid compatibility issues and allow future implementation flexibility, this mechanism is specified at a software (API) level. In other words, the actual GART table format may be abstracted to the API by a hardware abstraction layer (xe2x80x9cHALxe2x80x9d) or mini-port driver that is provided with the core logic chipset. While this API does not constrain the future partitioning of re-mapping hardware, the re-mapping function will typically be implemented in the core logic chipset.
The contiguous AGP graphics controller""s device addresses are mapped (translated) into corresponding physical addresses that reside in the computer system physical memory by using the GART table which may also reside in physical memory. The GART table is used by the core logic chipset to remap AGP device addresses that can originate from either the AGP, host, or PCI buses. The GART table is managed by a software program called a xe2x80x9cGART miniport driver.xe2x80x9d The GART miniport driver provides GART services for the computer software operating system.
What is needed to more fully and efficiently utilize the computer system and its physical memory when implementing AGP 3-D graphics requiring GART table translations is a system, method and apparatus for customizing the properties of each page of system memory associated with the GART table.
In light of the greater memory needs of increasingly complex applications, a GART table that implements greater than 32-bit addressing is desirable. The particular configuration of the GART table, including the number of bits used for addressing, would be dependent on the capabilities of the AGP device and the amount of system memory available for allocation to the AGP device.
Certain aspects commensurate in scope with the originally claimed invention are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In accordance with one aspect of the present invention, there is provided a computer system comprising a system processor to execute software instructions and generate graphics data, a system memory comprising a plurality of addressable storage locations in which the software instructions and the graphics data are stored, a graphics controller to generate video display data from the graphics data, and a core logic chipset coupled to the system processor, the system memory, and the graphics controller. The system further comprises a graphics address remapping table (GART) comprising a plurality of GART entries. Each of the GART entries comprises an address pointer to a corresponding addressable storage location of graphics data in the system memory. The core logic chipset uses the GART entries to remap the graphics data into a graphics device address space for use by the graphics controller in generating the video display data. Each GART entry comprises a plurality of bits, wherein the number of the bits of each entry is based on an addressing capability of the graphics controller.
In accordance with another embodiment, a core logic chipset for connecting a processor and a system memory to an accelerated graphics port (AGP) bus comprises a memory interface and control logic configured to connect to the system memory; a processor interface configured to connect to a processor; and an AGP data and control logic configured to connect to an AGP bus having an AGP device connected thereto. The AGP data and control logic is configured to use a GART comprising a plurality of GART entries, each of the plurality of GART entries comprising a plurality of bits, wherein the number of the bits of each GART entry is dependent on an addressing parameter.
In accordance with yet another embodiment of the invention, a method of creating a GART is provided. The method comprises determining an available amount of system memory, determining an amount of the available system memory to allocate to a graphics controller, and determining an addressing capability of the graphics controller. The method further comprises creating a GART to map a plurality of addressable storage locations in the system memory to a graphics address space for use by the graphics controller. The GART comprises a plurality of GART entries, each of which corresponds to one of the plurality of addressable storage locations. Each GART entry further comprises a plurality of bits, the number of which is dependent on at least one of the size of the available system memory to allocate to the graphics controller and the addressing capability of the graphics controller.